1. Field of the Invention
An embodiment of the present invention relates to memory devices and the related technologies thereof, and more particularly to a memory device with a built-in test function and a method for controlling the memory device as well as to a display device incorporating the memory device.
2. Description of the Related Art
These days, large-capacity memories are indispensable to the construction of systems. With increasing user requirements for systems which can realize further diversified functions with higher performance as well as in a further simplified form, there is an ever-growing demand for larger-capacity memories. However, with increases in memory capacity, problems such as a defect or failure in a memory cell naturally become noticeable. The presence of a defective or failed memory cell (hereinafter simply referred to as an “error cell”) would cause an abnormal operation or other drawbacks of a system.
A conventional method known as parity check has been employed for detecting an error cell. Depending on how to add a parity bit or a redundant bit to a predetermined bit length, the parity check may allow either only an error cell to be detected or an error cell to be not only detected but also corrected. For example, in Japanese Patent Laid-Open Publication No. Hei 10-49448, a technique is disclosed which utilizes the parity check to correct an error before a memory with redundancy is driven into an uncorrectable condition.